Low-consumption switched-capacitor circuit

ABSTRACT

A switched-capacitor circuit including at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one and the other of two terminals at a switching frequency. The circuit further includes a second capacitor connected to the first capacitor at a node; and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to switched-capacitor circuits and more specifically to switched-capacitor circuits of very high resolution.

2. Discussion of the Related Art

A switched-capacitor circuit comprises at least one capacitor having at least one armature alternately connected, at a switching frequency, to one or the other of two terminals by switches. In operation, the assembly formed by the capacitor and the associated switches has an equivalent resistance equal to the ratio of the switching period to the capacitance of the capacitor. Switched-capacitor circuits have many advantages. They enable to simulate a variable resistance which depends on the switching frequency. This is the reason why switched-capacitor circuits are especially used for the forming of filters having a cut-off frequency depending on the switching frequency. Further, for equivalent manufacturing technologies, a switched-capacitor circuit takes up a smaller surface area when integrated than that which would be taken up by an equivalent circuit formed with real resistors. Further, for equivalent manufacturing technologies, the capacitance of an integrated capacitor may be obtained with an accuracy greater than that of a resistor.

The current tendency is to form switched-capacitor circuits of very high resolution, that is, for which the signal-to-noise ratio or SNR is greater than some hundred decibels. For a conventional switched-capacitor circuit, this requires increasing the capacitances of the circuit capacitors up to values that can exceed several hundreds of picofarads. The capacitance increase of the capacitors translates as an unwanted increase of the total consumption of the switched-capacitor circuit. It is further generally difficult to integrate capacitors with high capacitances.

SUMMARY OF THE INVENTION

The present invention aims at a switched-capacitor circuit enabling to obtain a high SNR while maintaining a low consumption.

Another object of the present invention is the forming of a switched-capacitor circuit taking up a decreased surface area when it is made in integrated form.

For this purpose, the present invention provides a switched-capacitor circuit comprising at least one first capacitor and a circuit for switching at least one armature of the first capacitor alternately to one or the other of two terminals at a switching frequency. The circuit further comprises a second capacitor connected to the first capacitor at a node and a filtering circuit connecting the node to a virtual ground only for frequencies belonging to a frequency range.

According to an embodiment, the filtering circuit is capable of connecting the node to the virtual ground only for frequencies smaller than a threshold frequency greater than half the switching frequency.

According to an embodiment, the filtering circuit comprises an amplifier with differential inputs having an input connected to the node and having a main cut-off frequency, the threshold frequency of the filtering circuit corresponding to the main cut-off frequency.

According to an embodiment, the filtering circuit comprises at least one active filter comprising at least one active electronic component and at least one passive filter comprising at least one passive electronic component.

According to an embodiment, the capacitance of the second capacitor is smaller than the capacitance of the first capacitor.

According to an embodiment, the first capacitor comprises first and second armatures, the circuit comprising first, second, and third terminals; a first switch connecting the first terminal to the first armature of the first capacitor; a second switch connecting the second terminal to the first armature of the first capacitor; a third switch connecting the third terminal to the second armature of the first capacitor; and a fourth switch connecting the node to the second armature of the first capacitor, the first and fourth switches being controlled by a first binary signal and the second and third switches being controlled by a second binary signal, the first and second binary signals being non-overlapping.

According to an embodiment, the filtering circuit comprises an operational amplifier comprising an input connected to said node and an output connected to said input via the second capacitor, the threshold frequency of the filtering circuit corresponding to the cut-off frequency of the operational amplifier.

According to an embodiment, the second terminal is connected to a source of the reference voltage and the operational amplifier comprises an additional input connected to said source of the reference voltage.

According to an embodiment, the circuit further comprises a fifth switch across the second capacitor, the fifth switch being on, when the first and fourth switches are on, for a first time period and off for a second time period.

According to an embodiment, the circuit further comprises a third capacitor comprising third and fourth armatures, the operational amplifier comprising an additional input connected to an additional node and an additional output connected to the additional input via a fourth capacitor; fourth and fifth terminals; a sixth switch controlled by the first signal connecting the fourth terminal to the third armature of the third capacitor; a seventh switch controlled by the second signal connecting the fifth terminal to the fourth armature of the third capacitor; and an eighth switch controlled by the first signal connecting the additional node to the fourth armature of the third capacitor, the second terminal being located between the third armature of the third capacitor and the fifth switch.

The foregoing objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows a conventional embodiment of a switched-capacitor circuit;

FIG. 2 shows an electric circuit used to model the noise transfer function of the circuit of FIG. 1;

FIG. 3 schematically shows the variation of the noise power spectral density at the output of the circuit of FIG. 2;

FIGS. 4 and 5 are drawings respectively similar to FIGS. 1 and 2 of a variation of the circuit of FIG. 1;

FIG. 6 shows an electric circuit illustrating the operating principle of a switched-capacitor circuit according to the present invention;

FIG. 7 shows an embodiment of a switched-capacitor circuit according to the present invention;

FIG. 8 schematically shows the variation of the noise power spectral density at the output of the circuit of FIG. 7;

FIG. 9 shows an alternative embodiment of the circuit of FIG. 7;

FIGS. 10 and 12 show two conventional embodiments of an integrator with switched capacitors; and

FIGS. 11 and 13 show two embodiments of an integrator with switched capacitors according to the present invention.

DETAILED DESCRIPTION

For clarity, the same elements have been designated with the same reference numerals in the different drawings. Further, in the following description, the same reference is used to designate a capacitive element, or capacitor, and its capacitance, and the same reference is used to designate a resistive element, or resistor, and the value of its resistance. Further, “switched-capacitor circuit” is used in a general sense and may designate a circuit comprising a single capacitor having at least one of its armatures switched between two terminals.

FIG. 1 shows a conventional example of a switched-capacitor circuit 10 comprising an input terminal IN and an output terminal OUT. Call V_(IN) the voltage between terminal IN and a source of a reference voltage, for example, ground GND, and V_(OUT) the voltage between terminal OUT and ground GND. Circuit 10 comprises a capacitor C₀ having an armature connected to a node A and its other armature connected to a node B. Node A is connected to terminal IN via a switch SW₁ controlled by a control signal P₁. Node A is further connected to ground GND via a switch SW₂ controlled by a control signal P₂. Node B is connected to terminal OUT via a switch SW₃ controlled by signal P₂. Node B is further connected to ground GND via a switch SW₄ controlled by signal P₁. As an example, control signals P₁ and P₂ are binary signals alternating between a high state, noted “1”, and a low state, noted “0”. As an example, when signal P₁ is at “1” (signal P₂ at “0”), switches SW₁ and SW₄ are on and switches SW₂ and SW₃ are off. When signal P₁ is at “0” (signal P₂ at “1”), switches SW₁ and SW₄ are off and switches SW₂ and SW₃ are on. Signals P₁ and P₂ are non-overlapping, that is, they are not simultaneously in the state for which they control the turning-on of the associated switch (the high state in the present example). However, signals P₁ and P₂ may be simultaneously in the state for which they control the turning-off of the associated switches (the low state in the present example). As an example, signals P₁ and P₂ are complementary, that is, signal P₁ is in the low state when signal P₂ is in the high state and conversely. As an example, signals P₁ and P₂ are periodic with a frequency f_(S) (called switching frequency or sampling frequency hereafter) and a period T_(S). Call α the duty cycle of signal P₁. This means that over a time period T_(S), signal P₁ is in the high state for duration αT_(S) and in the low state for duration (α−1)T_(S), α being strictly smaller than 1. As an example, α is equal to ½.

Conventionally, circuit 10 is equivalent to a resistor R placed between terminals IN and OUT and having a resistance equal to:

R=T _(S) /C ₀=1/(C ₀ f _(S))   (1)

FIG. 2 shows a circuit 12 equivalent to the circuit 10 used to estimate the noise power spectral density at the output of circuit 10. In the case where switches SW₁ and SW₄ are formed of MOS transistors, it can be considered that, when switches SW₁ and SW₄ are on, circuit 10 is equivalent to a source S_(b) of a thermal noise in series with a resistor R_(ON) which corresponds to the internal resistance of MOS transistors in the on state. Voltage V_(IN) provided by noise source S_(b) is filtered by a low-pass filter formed by resistor R_(ON) and capacitor C₀ and having the following transfer function H:

$\begin{matrix} {H = \frac{1}{1 + {j\frac{f}{f_{C}}}}} & (2) \end{matrix}$

where f_(C) is the cut-off frequency of the low-pass filter and is equal to:

f _(C)=1/2πR _(ON) C ₀   (3)

It is considered that cut-off frequency f_(C) is much higher than sampling frequency f_(S), to obtain a proper charge of capacitor C₀.

The spectral power density S₀ of the noise provided by source S_(b) is equal to:

S₀=4kTR_(ON)   (4)

where k is Boltzmann's constant and T is temperature.

The noise power spectral density S₁ at the output of circuit 12 is equal to:

$\begin{matrix} {S_{1} = \frac{S_{0}}{1 + \left( \frac{f}{f_{C}} \right)^{2}}} & (5) \end{matrix}$

FIG. 3 schematically shows the variation of noise spectral density S₁. After sampling at frequency f_(S), noise power spectral density S₂ at the output of circuit 10 is provided by the following relation:

$\begin{matrix} {{S_{2}(f)} = {S_{0}{\sum\limits_{n = {- \infty}}^{n = {+ \infty}}\; \frac{1}{1 + \left( \frac{f - {nf}_{S}}{f_{C}} \right)^{2}}}}} & (6) \end{matrix}$

Call f_(N)/2 the maximum frequency of the useful signal to be transmitted. To respect Shannon's sampling criterion, frequency f_(N)/2 must be smaller than half sampling frequency f_(S). Relation (6) shows an aliasing in the useful band of the thermal noise due to the sub-sampling of the wide-band noise.

In practice, frequency f_(N) is much smaller than sampling frequency f_(S). As an example, frequency f_(S) is on the order of 1 MHz and frequency f_(N) is on the order of 1 kHz. An approached value of the RMS value of the noise voltage at the output of circuit V_(b) can be determined in a simple way. First, the sampling is not taken into account. The RMS value of noise voltage V_(b) at the output of circuit 12 is provided by the following relation:

$\begin{matrix} {V_{b} = {\sqrt{\int_{0}^{+ \infty}{{S_{1}(f)}\ {f}}} = {\sqrt{S_{0}{\int_{0}^{+ \infty}{\frac{1}{1 + \left( \frac{f}{f_{C}} \right)^{2}}{f}}}}\mspace{25mu} = {\sqrt{S_{0}f_{C}\frac{\pi}{2}}\mspace{25mu} = \sqrt{\frac{kT}{C_{0}}}}}}} & (7) \end{matrix}$

The noise being sampled at frequency f_(S), the noise is taken back into frequency band [0,f_(S)/2]. Further, the useful signal being in frequency band [0,f_(N)/2], only part of the noise is kept. The RMS value of the aliased noise voltage corresponds to:

$\begin{matrix} {V_{b} = \sqrt{\frac{kT}{C_{0}\frac{f_{S}}{f_{C}}}}} & (8) \end{matrix}$

A possibility to decrease the RMS value of noise voltage V_(b) is to increase capacitance C₀. Typically, to obtain an SNR greater than some hundred decibels, capacitance C₀ must be greater than some hundred picofarads. A disadvantage is that circuit 10 generally belongs to a circuit comprising other capacitors having values depending on C₀. For example, circuit 10 may belong to an integrator, possibly comprising another capacitor, called integration capacitor, having a capacitance that can be equal to approximately 10 times C₀. The integrated forming of capacitors having high capacitances, for example, greater than several hundreds of picofards, is difficult. Further, the increase in the capacitances of the capacitors of switched-capacitor circuits results in an increase in the total circuit consumption. This may be incompatible with applications for which the total circuit consumption is critical.

To increase the SNR of a switched-capacitor circuit without increasing the capacitance of the circuit capacitor, the applicant has first attempted to replace capacitor C₀ with two series-assembled capacitors to form a capacitive bridge.

FIG. 4 shows a switched-capacitor circuit 14 having a structure similar to that of circuit 10 of FIG. 1, with the difference that capacitor C₀ has been replaced with a capacitor C₁ and that a capacitor C₂ has been added between switch SW₄ and ground GND. Capacitance C₁ is greater than capacitance C₂. As an example, capacitance C₁ may be equal to ten times capacitance C₂. A node located between switch SW₄ and capacitor C₂ is designated as N.

FIG. 5 is an electric diagram 16 equivalent to circuit 14 when switches SW₁ and SW₄ are on and which illustrates the operation thereof Voltage V_(OUT) corresponds to the voltage across capacitor C₁. Call V′_(OUT) the voltage between node A and ground GND.

Transfer function H′ of circuit 16 is:

$\begin{matrix} {{H^{\prime}(f)} = {\frac{V_{OUT}}{V_{IN}} = {{\frac{V_{OUT}}{V_{OUT}^{\prime}}\frac{V_{OUT}^{\prime}}{V_{IN}}} = {\frac{C_{2}}{C_{2} + C_{1}}\frac{1}{1 + {j\frac{f}{f_{C}^{\prime}}}}}}}} & (9) \end{matrix}$

where f′_(C) is the cut-off frequency of the low-pass filter formed by resistor R_(ON) and capacitors C₁ and C₂. At low frequencies, transfer function H′ of circuit 16 is substantially equal to transfer function H of circuit 12 multiplied by attenuation factor C₂/(C₁+C₂). When capacitance C₁ is equal to 10 times capacitance C₂, the attenuation factor is 1/11. The capacitive bridge formed by capacitors C₁ and C₂ thus enables to decrease the contribution of noise across capacitor C₁. A 21-dB gain on the noise is thus obtained. However, the amplitude of the useful signal at low frequencies is also decreased by 21 decibels. The SNR of circuit 16 is thus not improved with respect to that of circuit 12.

The applicant has demonstrated that all of the useful low-frequency signal and only part of the high-frequency noise across capacitor C₁ could be obtained by connecting node N between capacitors C₁ and C₂ to a “virtual low-frequency ground”.

FIG. 6 shows a circuit 20 illustrating the principle of a virtual low-frequency ground. Node N is connected to a virtual low-frequency ground GND′ by a line 22 shown in dotted lines. Capacitor C₂, on the side opposite to node N, is connected to a circuit S_(C). For low frequencies, virtual ground GND′ is equivalent to ground GND. Everything happens as if node N was then directly connected to ground GND, short-circuiting capacitor C₂. For high frequencies, everything happens as if ground GND′ was not present and as if node B was normally connected to capacitor C₂. At high frequencies, circuit S_(C) maintains the armature of capacitor C₂ at a fixed voltage. The low-frequency components and especially the useful signal are thus only seen by capacitor C₁ while the high-frequency components (and, in particular, the high-frequency components of the wide-band thermal noise) are shared between capacitors C₁ and C₂. Advantage is thus taken of the attenuation of the high-frequency components of the noise without for the useful signal to be attenuated. Thereby, at the aliasing of the spectrum due to the sampling, the contribution of the high-frequency noise in the useful frequency band is decreased. Thereby, to obtain a given SNR, capacitance C₁ of circuit 20 according to the present invention may be smaller, for example, up to ten times, than capacitance C₀ of conventional circuit 10. The capacitances of capacitors C₁ and C₂ being low, the integrated manufacturing of circuit 20 is eased and the consumption of circuit 20 is decreased.

According to an embodiment the virtual “low frequency” ground is formed by a differential-input amplifier having an input connected to node N and having its other input connected to ground GND. Call main cut-off frequency the lowest frequency for which the amplifier gain falls by 3 dB with respect to the maximum amplifier gain. The amplifier may comprise active components (for example, an operational amplifier) and possibly passive components (resistor, capacitor, etc.).

FIG. 7 shows an embodiment of a switched-capacitor circuit 30 with a virtual ground. Circuit 30 comprises all the elements of circuit 14 of FIG. 4, but node N is connected to an inverting input I− of an operational amplifier 32. Non-inverting input I+ of operational amplifier 32 is connected to ground GND. Capacitor C₂ is provided between node N and output O+ of operational amplifier 32. Conventionally, operational amplifier 32 has a cut-off frequency f′_(C) on the order of from 1 to a few Megahertz, for example, 2 MHz, which is smaller than cut-off frequency f_(C) and is greater than half switching frequency f_(S) of switches SW₁ to SW₄. In the following description, frequencies smaller than cut-off frequency f′_(C) are called low frequencies and frequencies greater than cut-off frequency f′_(C) are called high frequencies

The operation of circuit 30 will be described when switches SW₁ and SW₄ are on. For frequencies smaller than cut-off frequency f′_(C), operational amplifier 32 operates normally. In particular, the voltages at inverting and non-inverting inputs I− and I+ of operational amplifier 32 are equal. Node N is thus effectively directly connected to ground GND. For frequencies greater than cut-off frequency f′_(C), operational amplifier 32 no longer operates properly, and everything happens as if it was not present, with output O+ being at high impedance. The high-frequency components are thus well distributed between capacitors C₁ and C₂.

FIG. 8 schematically shows an example of the variation of the noise power spectral density S₃ at the output of circuit 30 without taking the sampling into account. At low frequencies, the 1/f noise contribution of operational amplifier 32, also called flicker noise, can be observed. The amplitude of noise power spectral density S₃ at the output of circuit 30 decreases for frequencies greater than f′_(C). In the sampling, the high-frequency components of the thermal noise are aliased on interval [0, f_(S)/2]. Due to the fact that these high-frequency components have been attenuated, their contribution in useful band [0, f_(N)/2] is decreased.

Capacitance C₂ should advantageously be as low as possible with respect to C₁ to improve the attenuation of the high-frequency components. However, when switches SW₁ and SW₄ are on, voltage V_(S) at output O+ of the amplifier is equal to:

$\begin{matrix} {V_{S} = {{- \frac{C_{1}}{C_{2}}}V_{IN}}} & (10) \end{matrix}$

so that if the ratio of capacitances C₁ and C₂ is too high, operational amplifier 32 risks saturating.

FIG. 9 shows a switched-capacitor circuit 35 corresponding to a variation of circuit 30 of FIG. 7 in which a switch SW₅ is arranged across capacitor C₂. Switch SW₅ is controlled by a control signal P₃. During time αT_(S) for which signal P₁ is in the high state, signal P₃ is in the low state (switch SW₅ off) for a time period βαT_(S), β being strictly smaller than 1, and then in the high state (switch SW₅ off) for time period (1−β)αT_(S). During time period (1−α)T_(S) for which signal P₁ is in the low state, signal P₃ is in the high state (switch SW₅ off). Value β is selected so that capacitor C₂ does not have time to completely charge during time period βαT_(S) so that voltage V_(S) does not reach too high values, likely to cause the saturation of operational amplifier 32. For a conventional operational amplifier 32, and for a ratio C₁/C₂ equal to 10, β may be on the order of 1/2.

FIG. 10 shows a conventional example of application of switched-capacitor circuit 10 of FIG. 1 for the forming of an integrator 40. Terminal OUT of circuit 10 is connected to inverting input I′− of an operational amplifier 42. Non-inverting input I′+ of operational amplifier 42 is connected to ground GND. A capacitor C₃ is provided between inverting input I′− and an output terminal OUT′ of integrator 40. Output O′+ of operational amplifier 42 is connected to terminal OUT′.

The operation of integrator 40 will now be schematically described, assuming that voltage V_(OUT)′ is initially equal to V₀ and considering that signal P₁ is in the low state (signal P₂ in the high state). Switches SW₁ and SW₄ are then off and switches SW₂ and SW₃ are on. The charge stored in the right-hand armature of capacitor C₀ shown to the right of FIG. 10 is zero and the charge stored in the armature of capacitor C₃ shown to the left of FIG. 10 is equal to −C₃V₀.

When signal P₁ switches to the high state (P₂ in the low state), which corresponds to an accumulation phase, switches SW₁ and SW₄ are on and switches SW₂ and SW₃ are off. Capacitors C₀ and C₃ are separate. Charge −C₃V₀ remains trapped on the left-hand armature of capacitor C₃. The voltage at terminal OUT′ does not change. Further, capacitor C₀ charges and the right-hand armature of capacitor C₀ receives charge −C₀V_(IN).

When signal P₁ switches back to the low state (P₂ in the high state), which corresponds to an integration phase, capacitors C₀ and C₃ are connected to each other again. The output voltage of amplifier 42 then switches to V′_(OUT). The balance of the charges between capacitors C₀ and C₃ can be written as:

0−C ₃ V′ _(OUT) =−C ₀ V _(IN) −C ₃ V ₀   (11)

that is:

V′ _(OUT) =V ₀+(C ₀ /C ₃)V _(IN)   (12)

At each switching cycle of switches SW₁ to SW₄, voltage V′_(OUT) is equal to the sum of the value of the preceding cycle and of a term proportional to V_(IN). An integrator operation is thus obtained.

FIG. 11 shows an embodiment of an integrator 50 of the type shown in FIG. 10, implementing circuit 30 shown in FIG. 9. For this purpose, output terminal OUT of circuit 30 is connected to inverting input I′− of operational amplifier 42.

The operation of circuit 50 will now be described. When signal P₁ is in the high state during time αT_(S), that is, during the acquisition phase, switches SW₁ and SW₄ are on and switches SW₂ and SW₃ are off. Circuit 30 is not connected to operational amplifier 42 and operates as described previously. More specifically, switch SW₅ is off during time βαT_(S) and is on during time (1−β)αT_(S).

When signal P₁ is in the low state for time (1−α)T_(S), that is, during the integration phase, switches SW₁ and SW₄ are off and switches SW₂, SW₅, and SW₃ are on. Node B is no longer connected to node N and capacitor C₁ is connected to operational amplifier 42 identically to what has been previously described for capacitor C₀ of circuit 40. The high-frequency noise components which might be present during the integration phase are filtered by operational amplifier 42.

FIG. 12 shows a conventional embodiment of an integrator 60 having a differential structure. Integrator 60 comprises the elements of circuit 40 and, further, a capacitor C′₁ having an armature connected to an input terminal IN′ by a switch SW′₁ and is connected to switch SW₂. The other armature of capacitor C′₁ is connected to non-inverting input I′+ of differential amplifier 32 via a switch SW′₃ and to switch SW₄. Switch SW′₁ is controlled by signal P₁ and switch SW′₃ is controlled by switch P₂. Inverting input I′− of operational amplifier 42 is connected to an output terminal OUT″. A capacitor C′₃ is provided between non-inverting input I′+ and inverting output O′− of operational amplifier 42. The operation of integrator 60 is identical to that of integrator 40, the role of ground GND for integrator 40 being played, in this case, by the common-mode voltage of operational amplifier 42.

FIG. 13 shows the use of circuit 30 according to the present invention arranged in differential form for the forming of a positive differential integrator 70. Integrator 70 comprises the elements of circuit 60 and, further, a switch SW′₄ connecting capacitor C′₁ to non-inverting input I+ of operational amplifier 32. Integrator 70 further comprises a capacitor C′₂ arranged between non-inverting input I+ and inverting output O− of operational amplifier 32 and a switch SW′₅ arranged across capacitor C′₂. Switch SW′₅ is controlled by signal P₃. The operation of integrator 70 is identical to that of integrator 50, the role of ground GND for integrator 40 being played, in this case, by the common-mode voltage of operational amplifier 42.

The present invention enables to decrease the contribution of the high-frequency noise in the frequency band of the useful signal. Thereby, for a same SNR, it enables to decrease capacitance C₁ of circuit 30, 35 with respect to capacitance C₀ of circuit 10. In the present embodiment, capacitance C₁ may be ten times smaller than capacitance C₀. Further, when the switched-capacitor circuit is used to form an integrator, integration capacitance C₃ may be advantageously decreased with respect to a conventional circuit, for example, by a factor 10. More generally, the use of the switched-capacitor circuit according to the present invention in an electronic system may enable to decrease the capacitances of other capacitors of the electronic system. The present invention advantageously enables to decrease the surface area necessary to make switched-capacitor circuit 40 in integrated form, the surface area taken up by operational amplifier 32 being substantially equivalent to the surface area taken up by a capacitor having a capacitance of a few picofarads.

The present invention further provides a consumption gain on the order of from 7 to 8 with respect to a conventional switched-capacitor circuit. The circuit consumption is not exactly decreased by capacitance ratio C₁/C₂ since the consumption of operational amplifier 32 must be taken into account. Further, when the switched-capacitor circuit corresponds to a stage of an electronic system comprising several successive stages, the decrease in the input capacitance of the switched-capacitor circuit enables to decrease the constraints on the stage preceding the switched-capacitor circuit, for example, a pre-amplifier.

Specific embodiments of the present invention have been described. Different variations and modifications will occur to those skilled in the art. In particular, although an example of a switched-capacitor circuit comprising four switches SW₁ to SW₄ has been described, it should be clear that the present invention can apply to a switched-capacitor circuit in which a same armature of capacitor C₁ is switched between terminals IN and OUT, the other armature of capacitor C₁ being then connected to inverting input I− of operational amplifier 32.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto. 

1. A switched-capacitor circuit (30; 35) comprising at least one first capacitor (C1); and a circuit (SW₁) for switching a first armature of the first capacitor alternately towards an input (IN) and towards the ground (GND) respectively during first phases and during second phases of a switching signal at a frequency f_(S); a second capacitor (C₂) connected to the second armature of the first capacitor at a node (N); and a filtering circuit (32) connecting said node to a virtual ground (GND) only during the first phases of the switching signal, these first phases being the phases of signal storage of said input (IN) in the first capacitor (C₁).
 2. The circuit of claim 1, wherein the filtering circuit (32) is adapted for connecting the node to the virtual ground (GND) only for frequencies smaller than a threshold frequency (f′_(C)) greater than half the switching frequency (f_(S)).
 3. The circuit of claim 2, wherein the filtering circuit (32) comprises an amplifier with differential inputs having an input connected to the node (N) and having a main cut-off frequency, the threshold frequency (f′_(C)) of the filtering circuit corresponding to the main cut-off frequency.
 4. The circuit of claim 1, wherein the filtering circuit (32) comprises at least one active filter comprising at least one active electronic component and at least one passive filter comprising at least one passive electronic component.
 5. The circuit of claim 1, wherein the capacitance of the second capacitor (C₂) is smaller than the capacitance of the first capacitor (C₁).
 6. The circuit of claim 1, wherein the first capacitor (C₁) comprises first and second armatures, the circuit comprising: first, second, and third terminals (IN, GND, OUT); a first switch (SW₁) connecting the first terminal (IN) to the first armature of the first capacitor; a second switch (SW₂) connecting the second terminal (GND) to the first armature of the first capacitor; a third switch (SW₃) connecting the third terminal (OUT) to the second armature of the first capacitor; and a fourth switch (SW₄) connecting the node (N) to the second armature of the first capacitor, the first and fourth switches being controlled by a first binary signal (P₁) and the second and third switches being controlled by a second binary signal (P₂), the first and second binary signals being non-overlapping.
 7. The circuit of claim 6, wherein the filtering circuit comprises an operational amplifier (32) comprising an input (I−) connected to said node (N) and an output (O+) connected to said input via the second capacitor (C₂), the threshold frequency (f′_(C)) of the filtering circuit corresponding to the cut-off frequency of the operational amplifier.
 8. The circuit of claim 7, wherein the second terminal is connected to a source (GND) of the reference voltage and wherein the operational amplifier (32) comprises an additional input (I+) connected to said source of the reference voltage.
 9. The circuit of claim 7, further comprising a fifth switch (SW₅) across the second capacitor (C₂), the fifth switch being on, when the first and fourth switches (SW₁, SW₄) are on, for a first time period and off for a second time period.
 10. The circuit of claim 6, further comprising: a third capacitor (C′₁) comprising third and fourth armatures, the operational amplifier (32) comprising an additional input (I+) connected to an additional node and an additional output (O−) connected to the additional input via a fourth capacitor (C′₂); fourth and fifth terminals (IN′); a sixth switch (SW′₁) controlled by the first signal (P₁) connecting the fourth terminal (IN′) to the third armature of the third capacitor; a seventh switch (SW′₃) controlled by the second signal (P₂) connecting the fifth terminal to the fourth armature of the third capacitor; and an eighth switch (SW′₄) controlled by the first signal connecting the additional node to the fourth armature of the third capacitor, the second terminal being located between the third armature of the third capacitor and the fifth switch. 